Unless otherwise indicated herein, approaches described in this section are not prior art to the claims listed below and are not admitted to be prior art by inclusion in this section.
In high-speed packet switch design, ultra-high memory bandwidth is typically one of the most critical requirements for shared-buffer packet switches. To provide enough bandwidth for read and write operations, expensive multiple-port memory is commonly used to implement packet buffer. Conventional approaches use expensive multiple-port memory (e.g., two-write/two-read (2W2R) memory, two read-write (2RW) memory or four read-write (4RW) memory) or algorithmic memory to implement a high-speed packet buffer.
One example of an existing approach is shown in FIG. 6, which illustrates a packet buffer 600 of a two-port packet switch. The packet buffer 600 is built with a two-read/two-write (2R2W) memory capable of supporting two read (2R) operations and two write (2W) operations in the same clock cycle. Another example of an existing approach is shown in FIG. 7, which illustrates a packet buffer 700 of a two-port packet switch. The packet buffer 700 is built with multiple banks of 2RW memory units. Each of the 2RW memory unit is capable of supporting one of the following: two read operations in the same clock cycle, two write operations in the same clock cycle, or one read operation and one write operation in the same clock cycle. For write operations, the buffer management of packet buffer 700 allocates the memory banks with free cells and their read/write ports are not fully used (e.g., 2R or 1R+1W) in the same clock cycle. For example, when a first read port (TX0) is reading the first memory bank and a second read port (TX1) is reading the second memory bank, the buffer management may allocate a free cell from the first memory bank to a first write port (RX0) and allocate a free cell from the second memory bank to a second write port (RX1). When both TX0 and TX1 are reading the first bank, the buffer management may allocate a free cell from the second memory bank to RX0 and allocate a free cell from the third memory bank to RX1.
Nevertheless, conventional approaches such as those associated with packet buffer 600 and packet buffer 700 utilize expensive memory with relatively larger transistor counts per memory bit cell. Accordingly, drawbacks of these approaches include high cost and high power consumption due to larger transistor counts per memory bit cell.